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ESDR0502N Ultra Low Capacitance ESD Protection Array for High Speed Data Line Protection
The ESDR0502N ultra low capacitance TVS array is designed to protect high speed data lines from ESD. Ultra-low capacitance and high level of ESD protection makes this device well suited for use in USB 2.0 applications.
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Features
* * * * * * * * *
Low Capacitance (0.3 pF Typical Between I/O Lines and Ground) IEC 61000-4-2 Level 4 UL Flammability Rating of 94 V-0 These Devices are Pb-Free and are RoHS Compliant High Speed Communication Line Protection USB 2.0 High Speed Data Line and Power Line Protection Monitors and Flat Panel Displays MP3 Gigabit Ethernet
1
4
5
Typical Applications
UDFN6 MU SUFFIX CASE 517AA
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Operating Junction Temperature Range Peak Power Dissipation 8x20 ms @ TA = 25C (Note 1) Peak Power Current 8x20 ms @ TA = 25C (Note 1) Storage Temperature Range Lead Solder Temperature - Maximum (10 Seconds) IEC 61000-4-2 Contact (ESD) Symbol TJ Ppk Ipp Tstg TL ESD Value -40 to +125 100 3.0 -55 to +150 260 8.0 Unit C W A C C kV D M G
MARKING DIAGRAM
DM G = Specific Device Code* (Rotated 90 clockwise) = Date Code & Assembly Location = Pb-Free Device
PINOUT
GND NC NC 1 2 3 6 5 4 VBUS D+ D-
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Nonrepetitive current pulse (pin 6 to pin 1).
(Top View)
ORDERING INFORMATION
Device ESDR0502NMUTBG Package UDFN6 (Pb-Free) Shipping 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
November, 2009 - Rev. 0
1
Publication Order Number: ESDR0502N/D
ESDR0502N
ELECTRICAL CHARACTERISTICS
(TA = 25C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT IF VF Ppk C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Forward Current Forward Voltage @ IF Peak Power Dissipation Capacitance @ VR = 0 and f = 1.0 MHz IPP VC VBR VRWM IR VF IT V IF I
Uni-Directional TVS
*See Application Note AND8308/D for detailed explanations of datasheet parameters.
ELECTRICAL CHARACTERISTICS (TJ=25C unless otherwise specified)
Parameter Reverse Working Voltage Breakdown Voltage Reverse Leakage Current ESD Clamping Voltage Junction Capacitance Junction Capacitance Symbol VRWM VBR IR VC CJ CJ (Note 2) IT = 1 mA, (Note 3) VRWM = 5.5 V Per IEC61000-4-2 (Note 4) VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 1 MHz between I/O Pins See Figures 1 & 2 0.3 0.3 0.6 0.6 pF pF 6.0 1.0 Conditions Min Typ Max 5.5 Unit V V mA
2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000-4-2
Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000-4-2
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ESDR0502N
IEC 61000-4-2 Spec.
Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC61000-4-2 Waveform Ipeak 100% 90%
Level 1 2 3 4
Figure 3. IEC61000-4-2 Spec
ESD Gun
TVS
Oscilloscope
50 W Cable
50 W
Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D - Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger
100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr
systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.
PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms
40 t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
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ESDR0502N
APPLICATION INFORMATION
Protecting USB 2.0 Interfaces
The USB interface consists of Data (D- and D+) lines and a 5.5 V bus, which are all vulnerable to ESD and cable discharge events. Each ESDR0502N device will protect the four USB connections (VCC, D+, D-, and GND) of one USB port. When the voltage on the data lines exceed the bus
USB Controller
voltage (plus one diode drop), the internal rectifiers are forward biased conducting the transient current away from the protected controller chip. The TVS diode suppresses ESD strikes directly on the voltage bus and directs the surge to ground, protecting both the power and data pins.
USB Connector 1 D+ D- 2 3 6 5 4 VBUS D+ D-
ESDR0502N GND
Figure 6.
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ESDR0502N
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P CASE 517AA-01 ISSUE C
EDGE OF PACKAGE
D
A B L1
PIN ONE REFERENCE 2X
E
0.10 C
2X
DETAIL A Bottom View (Optional)
EXPOSED Cu MOLD CMPD
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D E e L L1 L2 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.20 BSC 1.00 BSC 0.40 BSC 0.30 0.40 0.00 0.15 0.40 0.50
0.10 C
(A3) A
A1
10X
0.08 C
SIDE VIEW A1
5X 1 3
SEATING PLANE
C L
L2
6X
b 0.10 C A B 0.05 C
NOTE 3
6
4
e BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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EEE EEE EEE
DETAIL B Side View (Optional) 0.40 PITCH
0.10 C
EE EE EE
TOP VIEW
A3
MOUNTING FOOTPRINT*
0.42
6X
0.22
6X
1.07
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ESDR0502N/D

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